View CXP84648_3307513.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

?1 cxp84632/84640/84648 e96309-st cmos 8-bit single chip microcomputer description the cxp84632/84640/84648 is a cmos 8-bit single chip microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time base timer, capture timer/counter, i 2 c bus interface, remote control reception circuit, pwm output, and 32khz timer/counter besides the basic configurations of 8-bit cpu, rom, ram, and i/o port. the cxp84632/84640/84648 also provides a sleep/ stop function that enables lower power consumption. features wide range instruction system (213 instructions) to cover various of data. 16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 250ns at 16mhz operation (4.5 to 5.5v) 333ns at 12mhz operation (3.0 to 5.5v) 122s at 32khz operation (2.7 to 5.5v) incorporated rom capacity 32k bytes (cxp84632) 40k bytes (cxp84640) 48k bytes (CXP84648) incorporated ram capacity 2048 bytes peripheral functions a/d converter 8 bits, 8 channels, successive approximation method (conversion time 20s/16mhz) serial interface srart-stop synchronization (uart), 1 channel incorporated buffer ram (auto transfer for 1 to 32 bytes), 1 channel incorporated 8-bit, 10-stage fifo (auto transfer for 1 to 10 bytes), 1 channel 8-bit clock syncronization (msb/lsb first selectable), 1 channel timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 16-bit capture timer/counter, 32khz timer/counter i 2 c bus interface remote control reception circuit 8-bit pulse measurement counter, 6-stage fifo pwm output circuit 12 bits, 2 channels interruption 21 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 80-pin plastic qfp piggyback/evaluation chip cxp84600 80-pin ceramic qfp perchase of sony's i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 80 pin qfp (plastic) structure silicon gate cmos ic
?2 cxp84632/84640/84648 ram 2048 bytes spc 700 cpu core interrupt controller a/d converter int3 int1 int0 int2 an0 to an7 8 rst v dd v ss tex extal xtal tx av ref av ss rxd txd pwm0 rom 32k/40k/48k bytes 2 clock generator/ system control rmc serial interface unit (ch0) buffer ram cs0 si0 so0 sck0 serial interface unit (ch1) si1 so1 sck1 fifo remocon in fifo port a 4 2 pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe3 pe4 to pe5 pf0 to pf6 pg0 to pg7 pi0 to pi7 port b port c port d port e port f port g port i ph0 to ph7 port h uart receiver uart transmitter uart baud rate generator 12 bit pwm generator 0 12 bit pwm generator 1 pwm1 i 2 c bus interface unit scl0 scl1 sda0 16 bit capture timer/counter 2 to sda1 adj 8 bit timer/counter 0 8 bit timer 1 ec0 cint ec1 32khz timer/counter prescaler/ time base timer 8 8 8 8 7 8 8 8 nmi int4 nmi serial interface unit (ch2) si2 so2 sck2 2 2 pf7 block diagram
?3 cxp84632/84640/84648 pin assignment (top view) pf3/sda0 pf4/pwm0 pf5/pwm1 pf6/txd pf7/rxd pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 ph0 ph1 ph2 pi4/int4 pi3/int3 pi2/int2 pi1/int1 pi0/int0 pe5/to/adj pe4 pe3/nmi pe2/rmc pe1/ec1 pe0/ec0 pb7/so1 pb6/si1 pb5/sck1 pb4/so0 pb3/si0 pb2/sck0 pb1/cs0 pb0/cint pa7/an7 pa6/an6 pa5/an5 pa4/an4 pa3/an3 ph3 ph4 ph5 ph6 ph7 rst extal xtal v ss tx tex av ss av ref pa0/an0 pa1/an1 pa2/an2 pf2/sda0 pf1/scl1 pf0/scl0 pg7 pg6 pg5 pg4 nc v dd pg3 pg2 pg1 pg0 pi7/so2 pi6/si2 pi5/sck2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 1 note) nc (pin 73) must be connected v dd .
?4 cxp84632/84640/84648 (port f) lower 7 bits are for output; of which lower 4 bits are large current (12ma) n-ch open drain output. the uppermost bit (pf7) is for input. (8pins) pin description pin code i/o functions i/o/analog input pa0/an0 to pa7/an7 (port a) 8-bit i/o port. i/o can be set in a unit of signle bits. incorporation of the pull- up resistance can be set through the software in a unit of 4 bits. (8 pins) analog inputs to a/d converter. (8 pins) i/o pc0 to pc7 (port c) 8-bit i/o port. i/o can be set in a unit of single bits. capable of driving 12ma sync current. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) i/o pd0 to pd7 (port d) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull- up resistor can be set through the software in a unit of 4 bits. (8 pins) input/input input/input input/input input/input output output/output/ output output/i/o output/i/o output/output output/output output/output input/input pe0/ec0 pe1/ec1 pe2/rmc pe3/nmi pe4 pe5/to/ adj pf0/scl0 pf1/scl1 pf2/sda0 pf3/sda1 pf4/pwm0 pf5/pwm1 pf6/txd pf7/rxd (port e) 6-bit port. lower 4 bits are for inputs; upper 2 bits are for outputs. (6 pins) external event inputs for timer/counter. (2 pins) remote control reception circuit input. non-maskable interruption request input. rectangular wave output for 16-bit timer/counter. output for 32khz oscillation frequency division. i/o/input i/o/input i/o/i/o i/o/input i/o/output i/o/i/o i/o/input i/o/output pb0/cint pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 (port b) i/o can be set in a unit of single bits for lower 7 bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) external capture input to 16-bit timer/counter. chip select input for serial interface (ch0). serial clock i/o (ch0). serial data input (ch0). serial data output (ch0). serial clock i/o (ch1). serial data input (ch1). serial data output (ch1). pwm outputs. (2pins) uart transmission data output. uart reception data input. transfer clock i/o for i 2 c bus interface. (2pins) transfer data i/o for i 2 c bus interface. (2pins)
?5 cxp84632/84640/84648 serial clock i/o. (ch2) serial data input. (ch2) serial data output. (ch2) pin code i/o functions i/o pg0 to pg7 (port g) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull- up resistor can be set through the software in a unit of 4 bits. (8 pins) i/o ph0 to ph7 (port h) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull- up resistor can be set through the software in a unit of 4 bits. (8 pins) i/o/input pi0/int0 to pi4/int4 i/o/i/o i/o/input i/o/output pi5/sck2 pi6/si2 pi7/so2 input crystal connectors for system clock oscillation. when the clock is supplied externally, input to extal; opposite phase clock should be input to xtal. extal output xtal input crystal connectors for 32khz timer/counter clock oscillation. for usage as event counter, input to tex, and open tx. tex output tx input low-level active, system reset. rst nc. under normal operating conditions, connect to v dd . nc input reference voltage input for a/d converter. av ref a/d converter gnd. avss positive power supply. v dd gnd. vss (port i) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) external interruption request inputs. (5 pins)
?6 cxp84632/84640/84648 port b data bus rd (port b, i) aaaa aaaa aa aa port b, i direction ip aa aa aaaa port b, i data aaaa aaaa pull-up resistance ??when reset ??when reset * schmitt input cint cs0 si0 si1 * pull-up transistors approx. 100k w 8 pins hi-z hi-z when reset pa0/an0 to pa7/an7 pb0/cint pb1/cs0 pb3/si0 pb6/si1 pi6/si2 port b data bus rd (port b, i) a a ip a a aaaaa aaaaa port b, i function selection ??when reset * schmitt input sck in aaaa aaaa port b, i data aaaa aaaa port b, i direction ??when reset aaaa aaaa pull-up resistance ??when reset sck out serial clock output enable * pull-up transistors approx. 100k w 5 pins 3 pins hi-z pb2/sck0 pb5/sck1 pi5/sck2 data bus rd (port a) aaaa aa port a direction ip aa aa aaaa aaaa port a data aaaa aaaa pull-up resistance a aa a aaaa port a function selection input protection circuit ??when reset ??when reset ??when reset input multiplexer a/d converter * pull-up transistors approx. 100k w * i/o circuit format for pins port a pin circuit format port i port i
?7 cxp84632/84640/84648 3 pins hi-z pin when reset circuit format pb4/so0 pb7/so1 pi7/so2 pc0 to pc7 8 pins 5 pins hi-z pe0/ec0 pe1/ec1 pe2/rmc pe3/nmi pf7/rxd a ip a schmitt input rd (port e, f) data bus ec0, ec1, rmc, nmi, rxd data bus rd (port c) aaaa aaaa aa aa port c direction ip aa aa aaaa port c data aaaa aaaa pull-up resistance ??when reset ??when reset * 1 large current 12ma * 2 pull-up transistors approx. 100k w * 2 * 1 data bus rd (port b, i) aa ip aa aa aaaaa port b, i function selection ??when reset * aaaa aaaa port b, i data aaaa aaaa port b, i direction ??when reset aaaa pull-up resistance so serial data output enable ??when reset * pull-up transistors approx. 100k w port e port b port c 1 pin high level pe4 data bus rd (port e) aa aa aaaa aaaa port e data ??when reset port e port f port i hi-z
?8 cxp84632/84640/84648 1 pin pin when reset circuit format pe5/to/adj 24 pins hi-z pd0 to pd7 pg0 to pg7 ph0 to ph7 data bus rd (port d, g, h) aa aa ip aa aa aaaaa port d, g, h data ??when reset * aaaaa aaaaa port d, g, h direction aaaaa aaaaa pull-up resistance ??when reset * pull-up transistors approx. 100k w port d port g port h 5 pins hi-z data bus rd (port i) aa aa ip aa aa aaaa port i data ??when reset * aaaa aaaa port i direction aaaa aaaa pull-up resistance ??when reset int0 int1 int2 int3 int4 * pull-up transistors approx. 100k w port i pi0/int0 to pi4/int4 aa aa aaaaa port e data * 1 adj signals are frequency dividing output for 32khz oscillation frequency adjustment. adj2k provides usage as buzzer output. * 2 pull-up transistor approx. 150k w aaaaaa aaaaaa port e function selection (lower) ?0?when reset aaaaaa port e function selection (upper) to adj16k * 1 adj2k * 1 to output enable 01 10 11 00 mpx internal reset signal * 2 ??when reset high level with approx. 150k resistor when reset () port e
?9 cxp84632/84640/84648 4 pins pin when reset circuit format pf6/txd hi-z pf0/scl0 pf1/scl1 pf2/sda0 pf3/sda1 scl, sda (to i 2 c circuit) aa aa aaa aaa port f data (??when reset) scl, sda i 2 c output enable * large current 12ma to internal i 2 c pin (scl1 for scl0) bus sw ??when reset aa aa ip schmitt input * hi-z ph0 to ph7 8 pins aa aa standby release aaaa aaaa port h data aa aa ip data bus rd (port h) aaaa aaaa port h direction aa aa edge detection rd (port h direction) ??when reset data bus aa aa aaaaa aaaaa port f output selection ??when reset uart transmission circuit data bus rd (port f) aaaaa aaaaa port f data ??when reset high level high level aa aa data bus rd (port f) aaaaa aaaaa port f output selection ??when reset aaaaa aaaaa port f data pwm ??when reset port f 2 pins 1 pin pf4/pwm0 pf5/pwm1 port f port f port h
?10 cxp84632/84640/84648 2 pins pin when reset circuit format extal xtal aa aa ip aa extal xtal diagram shows circuit composition during oscillation. feedback resistor is removed during stop, and xtal becomes high level. a ip 2 pins oscillation tex tx aa aa ip aa tex diagram shows circuit composition during oscillation. a ip when the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and tex and tx become low level and high level respectively. tx 1 pin low level rst aa aa schmitt input pull-up resistor mask option op a a ip oscillation
input voltagte output voltage high level output current high level total output current low level total output current operating temperature storage temperature allowable power dissipation ?11 cxp84632/84640/84648 * 1 v in and v out must not exceed v dd + 0.3v. * 2 the large current output is for each pin of port c (pc), port f0 (pf0) to port 3 (pf3). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. v dd av ss v in v out i oh i oh i ol i olc i ol topr tstg p d low level output current supply voltage ?.3 to +7.0 ?.3 to +0.3 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ? ?0 15 20 100 ?0 to +75 ?5 to +150 600 v v v v ma ma ma ma ma ? ? mw output (value per pin) total for all output pins all pins excluding large current outputs (value per pin) large current outputs (value per pin) * 2 total for all output pins item symbol rating unit remarks absolute maximum ratings (vss = 0v reference)
?12 cxp84632/84640/84648 high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 v dd v dd v dd v dd + 0.3 v dd + 0.2 0.3v dd 0.2v dd 0.2v dd 0.4 0.2 +75 v v v v v v v v v v ? v v v v v item symbol min. 4.5 3.0 5.5 5.5 max. unit remarks fc = 16mhz or less guaranteed operation range for 1/2 and 1/4 frequency dividing clock. fc = 12mhz or less 2.7 2.7 2.5 0.7v dd 0.8v dd 0.8v dd v dd ?0.4 v dd ?0.2 0 0 0 ?.3 ?.3 ?0 v ih v ihs v ihex v il v ils v ilex topr guaranteed operation range for 1/16 frequency dividing clock or sleep mode guaranteed operation range by tex clock guaranteed data hold operation range during stop * 1 , * 5 * 1 , * 6 hysteresis input * 2 extal pin * 3 , * 5 tex pin * 4 , * 5 extal pin * 3 , * 6 tex pin * 4 , * 6 * 1 , * 5 * 1 , * 6 hysteresis input * 2 extal pin * 3 , * 5 tex pin * 4 , * 5 extal pin * 3 , * 6 tex pin * 4 , * 6 v dd * 1 normal input port (each pin of pa, pb4, pb7, pc, pf0 to pf4, pg, ph and pi7) * 2 each pin of rst, cint, cs0, sck0, sck1, sck2, si0, si1, si2, ec0, ec1, rmc, nmi, rxd, int0, int1, int2, int3 and int4 * 3 it is specified only when the external clock is input. * 4 it is specified only when the external event count clock is input. * 5 this case applies to the range of 4.5 to 5.5v supply voltage (v dd ). * 6 this case applies to the range of 3.0 to 5.5v supply voltage (v dd ). recommended operating conditions (vss = 0v reference)
?13 cxp84632/84640/84648 v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 4.5v, i ol = 3.0ma v dd = 4.5v, i ol = 4.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 0.4v v dd = 4.5v, v il = 4.0v v dd = 5.5v v i = 0, 5.5v v dd = 5.5v v oh = 5.5v v dd = 4.5v v scl0 = v scl1 = 2.25v v sda0 = v sda1 = 2.25v high level output voltage i/o lealage current 4.0 3.5 0.5 ?.5 0.1 ?.1 ?.5 ?.78 v v v v v v v ? ? ? ? ? ? ? ? ? pc, pf0 to pf3 pf0 to pf3 (scl0, scl1, sda0, sda1) pa to pd, pe4, pe5, pf4, pf5, pf6, pg to pi extal tex rst * 1 pa to pd * 2 , pg to pi * 2 item symbol pins conditions min. pa to pd * 2 , pg to pi * 2 , rst * 1 i iz i il v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current typ. 0.4 0.6 1.5 0.4 0.6 40 ?0 10 ?0 ?00 ?5 ?0 10 120 max. unit dc characteristics supply voltage (v dd ) 4.5 to 5.5v electrical characteristics (ta = ?0 to +75?, vss = 0v reference) open drain output leakage current (n-ch tr off state) i loh pf0 to pf3 (scl0, scl1, sda0, sda1) i 2 c bus switch connection impedance (output tr off state) r bs scl0: scl1 sda0: sda1
?14 cxp84632/84640/84648 supply current * 3 item symbol pins conditions min. 31 40 8 100 30 ? ? 50 ma ma ? 2.5 10 10 pa to pc, pe0 to pe5, pf to pi, extal, tex, rst clock 1mhz 0v for all pins excluding measured pins v dd = 5.5v, 16mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation; and termination of 16mhz oscillation (c 1 = c 2 = 47pf) 1/2 frequency dividing clock operation v dd i dd1 i dd2 i dds1 i dds2 i dds3 c in typ. max. unit * 1 rst specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. * 2 pa to pd, and pg to pi specify the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. * 3 when all pins are open. v dd = 5.5v, 16mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation; and termination of 16mhz oscillation (c 1 = c 2 = 47pf) sleep mode stop mode v dd = 5.5v, termination of 16mhz and 32khz crystal oscillation input capacity pf 20 10
?15 cxp84632/84640/84648 v dd = 3.0v, i oh = ?.15ma v dd = 3.0v, i oh = ?.5ma v dd = 3.0v, i ol = 1.2ma v dd = 3.0v, i ol = 1.6ma v dd = 3.0v, i ol = 5.0ma v dd = 3.0v, i ol = 2.0ma v dd = 3.0v, i ol = 2.5ma v dd = 3.6v, v ih = 3.6v v dd = 3.6v, v il = 0.3v v dd = 3.6v, v il = 3.6v v dd = 3.6v, v il = 0.4v v dd = 3.6v, v il = 0.3v v dd = 3.0v, v il = 2.7v v dd = 3.6v v i = 0, 3.6v v dd = 3.6v v oh = 3.6v v dd = 3.0v v scl0 = v scl1 = 1.5v v sda0 = v sda1 = 1.5v high level output voltage i/o lealage current 2.7 2.3 0.3 ?.3 0.1 ?.1 ?.9 ?.0 v v v v v v v ? ? ? ? ? ? ? ? ? pc, pf0 to pf3 pf0 to pf3 (scl0, scl1, sda0, sda1) pa to pd, pe4, pe5, pf4, pf5, pf6 extal tex rst * 1 pa to pd * 2 , pg to pi * 2 item symbol pins conditions min. pa to pd * 2 , pg to pi * 2 , rst * 1 i iz i il v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current typ. 0.3 0.5 1 0.3 0.5 20 ?0 10 ?0 ?00 ?0 ?0 10 300 max. unit dc characteristics supply voltage (v dd ) 3.0 to 3.6v electrical characteristics (ta = ?0 to +75?, vss = 0v reference) open drain output leakage current (n-ch tr off state) i loh pf0 to pf3 (scl0, scl1, sda0, sda1) i 2 c bus switch connection impedance (output tr off state) r bs scl0: scl1 sda0: sda1
?16 cxp84632/84640/84648 supply current * 3 item symbol pins conditions min. 11 25 ma ma ? 0.5 2.5 10 clock 1mhz 0v for all pins excluding measured pins v dd = 3.6v, 12mhz crystal oscillation (c 1 = c 2 = 15pf) 1/2 frequency dividing clock operation v dd i dd1 i dds1 i dds3 c in typ. max. unit v dd = 3.6v, 12mhz crystal oscillation (c 1 = c 2 = 15pf) sleep mode stop mode v dd = 3.6v, termination of 16mhz and 32khz crystal oscillation input capacity pf 20 10 pa to pc, pe0 to pe5, pf to pi, extal, tex, rst * 1 rst specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. * 2 pa to pd, and pg to pi specify the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. * 3 when all pins are open.
?17 cxp84632/84640/84648 extal t xh t xl t cf t cr 0.4v (v dd = 4.5 to 5.5v) v dd ?0.4v (v dd = 4.5 to 5.5v) 1/fc v dd ?0.3v 0.3v aaaa a aa a aaaa aaaa a aa a aaaa crystal oscillation ceramic oscillation extal xtal external clock extal xtal 74hc04 c 1 c 2 aaaa a aa a aaaa 32khz clock applied condition crystal oscillation tex tx c 1 c 2 tex ec0 ec1 t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr fig. 2. clock applied conditions fig. 1. clock timing fig. 3. event count clock timing ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise time, fall time event count input clock pulse width event count input clock rise time, fall time system clock frequency event count input clock input pulse width event count input clock rise time, fall time f c t xl t xh t cr t cf t eh t el t er t ef f c t tl t th t tr t tf xtal extal extal extal ec0 ec1 ec0 ec1 tex tx tex tex mhz ns ns ns ms khz ? ms item symbol pin conditions min. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock applied condition) fig. 3 fig. 3 1 1 28 37.5 4 t sys * 1 10 typ. 32.768 max. 16 12 200 20 20 (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) * 1 t sys indicates the three values below according to the upper two bits (cpu clock selection) of the control clock register (clc: 00fe h ). t sys [ns] = 2000/fc (upper two bits = ?0?, 4000/fc (upper two bits = ?1?, 16000/fc (upper two bits = ?1? v dd = 4.5 to 5.5v v dd = 4.5 to 5.5v
note 1) t sys indicates three values according to the contents of the clock control register (clc; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = ?1?, 16000/fc (upper 2 bits = ?1? note 2) cs, sck, si and so represent cs0, sck0, si0 and so0, respectively. note 3) the load of sck output mode and so output delay time is 50pf + 1ttl. ?18 cxp84632/84640/84648 (2) serial transfer (ch0) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) cs ? sck delay time cs - ? sck floating delay time cs ? so delay time cs ? so floating delay time cs high level width t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc ?100 t sys + 100 200 2 t sys + 100 100 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns item symbol pin condition min. max. unit chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck cycle time sck high and low level widths si input setup time (against sck - ) si input hold time (against sck - ) sck ? so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0
?19 cxp84632/84640/84648 note 1) t sys indicates three values according to the contents of the clock control register (clc; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = ?1?, 16000/fc (upper 2 bits = ?1? note 2) cs, sck, si and so represent cs0, sck0, si0 and so0, respectively. note 3) the load of sck output mode and so output delay time is 50pf. serial transfer (ch0) (ta = ?0 to +75?, v dd = 3.0 to 3.6v, vss = 0v reference) cs ? sck delay time cs - ? sck floating delay time cs ? so delay time cs ? so floating delay time cs high level width t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc ?150 t sys + 100 200 2 t sys + 100 100 t sys + 250 t sys + 200 t sys + 250 t sys + 200 2 t sys + 250 125 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns item symbol pin condition min. max. unit chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck cycle time sck high and low level widths si input setup time (against sck - ) si input hold time (against sck - ) sck ? so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0
?20 cxp84632/84640/84648 fig. 4. serial transfer ch0 timing cs0 sck0 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0
?21 cxp84632/84640/84648 serial transfer (ch1, ch2) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) item symbol pin min. max. unit condition sck cycle time sck high and low level widths si input setup time (against sck - ) si input hold time (against sck - ) sck ? so delay time t kcy t kh t kl t sik t ksi t kso sck1 sck2 sck1 sck2 si1 si2 si1 si2 so1 so2 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 2 t sys + 200 16000/fc t sys + 100 8000/fc ?50 100 200 t sys + 200 100 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns note 1) t sys indicates three values according to the contents of the clock control register (clc; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = ?1?, 16000/fc (upper 2 bits = ?1? note 2) sck, si and so represent sck1, si1, and so1, respectively for ch1; they represent sck2, si2 and so2, respectively for ch2. note 3) the load of sck1 and sck2 output modes and so1 and so2 output delay times is 50pf+1ttl. serial transfer (ch1, ch2) (ta = ?0 to +75?, v dd = 3.0 to 3.6v, vss = 0v reference) item symbol pin min. max. unit condition sck cycle time sck high and low level widths si input setup time (against sck - ) si input hold time (against sck - ) sck ? so delay time t kcy t kh t kl t sik t ksi t kso sck1 sck2 sck1 sck2 si1 si2 si1 si2 so1 so2 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 2 t sys + 200 16000/fc t sys + 100 8000/fc ?150 100 200 t sys + 200 100 t sys + 250 125 ns ns ns ns ns ns ns ns ns ns note 1) t sys indicates three values according to the contents of the clock control register (clc; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = ?1?, 16000/fc (upper 2 bits = ?1? note 2) sck, si and so represent sck1, si1, and so1, respectively for ch1; they represent sck2, si2 and so2, respectively for ch2. note 3) the load of sck1 and sck2 output modes and so1 and so2 output delay times is 50pf.
?22 cxp84632/84640/84648 fig. 5. serial transfer ch1 and ch2 timing t kcy t kl t kh 0.2v dd 0.8v dd t sik t ksi t kso input data output data 0.2v dd 0.8v dd 0.2v dd 0.8v dd sck1 sck2 si1 si2 so1 so2
?23 cxp84632/84640/84648 convertion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian v zt * 1 v ft * 2 i ref av ref an0 to an7 ta = 25? v dd = av ref = 5.0v v ss = av ss = 0v operation mode sleep mode stop mode 32khz operation mode linearity errror zero transition voltage full-scale transition voltage resolution av ref current av ref i refs ? ? v v v v dd v dd av ref 1.0 0.7 ma 10 ? 0.6 160/f adc * 3 12/f adc * 3 v dd ?0.5 v dd ?0.3 0 item symbol pin condition min. typ. max. unit bits (3) a/d converter characteristics (ta = ?0 to +75?, v dd = 3.0 to 5.5v, av ref = 2.7 to v dd , vss = av ss = 0v reference) 8 3 lsb 70 mv 5030 10 4970 ?0 4910 mv fig.6. definition of a/d converter terms analog input linearity error v ft v zt 00 h 01 h fe h ff h digital conversion value 00 ( f = f ex /2) 01 ( f = f ex /4) 11 ( f = f ex /16) f adc = f c /2 f adc = f c /4 f adc = f c /16 0( f /2 selection) cks pck1, pck0 f adc = f c f adc = f c /2 f adc = f c /8 1( f selection) linearity errror zero transition voltage full-scale transition voltage v zt * 1 v ft * 2 ta = 25? v dd = av ref = 3.3v v ss = av ss = 0v lsb mv mv ma 0.4 v dd = 4.5 to 5.5v v dd = 3.0 to 3.6v ?0 3215 6.5 3280 70 3345 ? v dd = 5.5v v dd = 3.6v * 1 v zt : value at which the digital conversion value changes from 00 h to 01 h and vice versa. * 2 v ft : value at which the digital conversion value changes from fe h to ff h and vice versa. * 3 f adc indicates the below values due to the contents of bit 6 (cks) of the a/d control register (adc: 00f9 h ) and bits 7 (pck1) and 6 (pck0) of the clock control register (clc: 00fe h ).
?24 cxp84632/84640/84648 external interruption high, low level width reset input low level width int0 int1 int2 int3 int4 nmi rst 1 32/fc ? ? item symbol pin condition min. max. unit t ih t il t rsl (4) interruption, reset input 0.2v dd 0.8v dd t ih t il t il t ih int0 int1 int2 int3 int4 nmi (nmi is specified only for the falling edge) fig. 7. interruption input timing t rsl 0.2v dd rst fig. 8. rst input timing (ta = ?0 to +75?, v dd = 3.0 to 5.5v, vss = 0v reference)
?25 cxp84632/84640/84648 (5) i 2 c bus timing (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) item scl clock frequency bus-free time before starting transfer hold time for starting transfer clock low level width clock high level width setup time for repetitive transfers data bold time data setup time sda, scl rise time sda, scl fall time setup time for transfer completion f slc t buf t hd; sta t low t high t su; sta t hd; dat t su; dat t r t f t su; sto scl sda, scl sda, scl scl scl sda, scl sda, scl sda, scl sda, scl sda, scl sda, scl 0 4.7 4.0 4.7 4.0 4.7 0 * 1 250 4.7 100 1 300 khz ? ? ? ? ? ? ns ? ns ? symbol pin condition min. max. unit * 1 the data hold time must exceed 300ns because the scl rise time (300ns max.) is not taken into consideration. fig. 9. i 2 c bus transfer timing p st t su; sto t su; sta t hd; sta t su; dat t high t hd; dat t f t r t low t hd; sta s p t buf sda scl fig. 10. recommended circuit example for i 2 c device i 2 c device i 2 c device r s r s r s r s r p r p sda0 (or sda1) scl0 (or scl1) pull-up resistors (r p ) must be connected to sda0 (or sda1) and scl0 (or scl1). serial resistance (rs = 300 or less) of sda0 (or sda1) and scl0 (or scl1) reduces spike noise caused by crt flash-over.
?26 cxp84632/84640/84648 appendix fig. 11. spc700 series recommended oscillation circuit aaaaa a aaa a aaaaa extal xtal c 1 c 2 rd (i) aaaaa a aaa a aaaaa tex tx c 1 c 2 rd (ii) manufacturer river eletec co., ltd. kinseki ltd. model hc-49/u03 hc-49/u (-s) p3 fc (mhz) 8.00 10.00 12.00 8.00 10.00 12.00 12 12 12 12 0 16.00 30 18 470k (ii) 32.768khz 10 5 16 (12) 10 16.00 5 16 (12) 16 (12) 16 (12) 0 0 0 c 1 (pf) c 2 (pf) rd ( ) circuit example (i) (i) reset pin pull-up resistor non-existent existent item content mask option table
?27 cxp84632/84640/84648 characteristics curve v dd ?upply voltage [v] 34 56 0.01 (10a) 0.1 (100a) 1.0 i dd ?upply current [ma] i dd vs. v dd (fc = 16mhz, ta = 25?, typical) 1/2 frequency mode 1/4 frequency mode 1/16 frequency mode 32khz mode (instruction) sleep mode 32khz sleep mode i dd vs. fc (v dd = 5.0v, ta = 25?, typical) fc?ystem clock [mhz] i dd ?upply current [ma] 1 0 1/4 frequency mode 1/16 frequency mode sleep mode 5101516 10 20 30 i dd ?upply current [ma] i dd vs. v dd (fc = 12mhz, ta = 25?, typical) 0.05 (50a) 5.0 10.0 0.5 v dd ?upply voltage [v] 3456 0.01 (10a) 0.1 (100a) 1.0 0.05 (50a) 5.0 10.0 0.5 1/2 frequency mode 1/4 frequency mode 1/16 frequency mode sleep mode 1/2 frequency mode i dd vs. fc (v dd = 3.3v, ta = 25?, typical) fc?ystem clock [mhz] i dd ?upply current [ma] 1 0 1/4 frequency mode sleep mode 5101516 10 20 30 1/2 frequency mode 1/16 frequency mode 50.0 50.0
?28 cxp84632/84640/84648 package outline unit: mm package structure sony code eiaj code jedec code qfp-80p-l01 * qfp080-p-1420-a package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy 1.6g 23.9 0.4 20.0 ?0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 ?0.1 + 0.15 14.0 ?0.1 + 0.4 17.9 0.4 16.3 0.1 ?0.05 + 0.2 2.75 ?0.15 + 0.35 0.8 0.2 0.15 ?0.05 + 0.1 80pin qfp (plastic) m 0.12 0.15 0?to 10 detail a a

▲Up To Search▲

Price & Availability of CXP84648

	To Download CXP84648 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .